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Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV

Journal of the Brazilian Computer Society volume 13, pages 25–36 (2007)Cite this article

Abstract

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

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Authors and Affiliations

  1. Informatics Institute, Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Campus do Vale, Bloco IV, P.O.Box 15064, Zip 91501-970, Porto Alegre, RS, BRAZIL

    Luciano V. Agostini, Arnaldo P. Azevedo Filho, Wagston T. Staehler, Vagner S. Rosa, Bruno Zatt, Ana Cristina M. Pinto, Roger Endrigo Porto & Sergio Bampi

  2. Informatics Department, Federal University of Pelotas, P.O.Box 354, Zip 96010-900, Pelotas, RS, BRAZIL

    Luciano V. Agostini

  3. Electrical Engineering Department, Federal University of Rio Grande do Sul, Av. Osvaldo Aranha, 103, Zip 90035-190, Porto Alegre, RS, BRAZIL

    Altamiro A. Susin

Authors
  1. Luciano V. Agostini
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  2. Arnaldo P. Azevedo Filho
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  3. Wagston T. Staehler
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  4. Vagner S. Rosa
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  5. Bruno Zatt
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  6. Ana Cristina M. Pinto
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  7. Roger Endrigo Porto
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  8. Sergio Bampi
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  9. Altamiro A. Susin
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Open Access This article is distributed under the terms of the Creative Commons Attribution 2.0 International License ( https://creativecommons.org/licenses/by/2.0 ), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Agostini, L.V., Azevedo Filho, A.P., Staehler, W.T. et al. Design and FPGA prototyping of a H.264/AVC main profile decoder for HDTV. J Braz Comp Soc 13, 25–36 (2007). https://doi.org/10.1007/BF03192399

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