Table 6 Results of the RTM algorithm execution on GiDEL platform
From: An inter-FPGA communication bus with error detection and dynamic clock phase adjustment
Problem | Single FPGA | 4 FPGAs optimal | 4 FPGAs real |
|---|---|---|---|
size | performance | performance | performance |
| Â | (GSamples/s) | (GSamples/s) | (GSamples/s) |
400 × 216 × 216 | 0.42 | 1.68 | 1.65 |
300 × 288 × 288 | 0.35 | 1.42 | 1.38 |
1000 × 432 × 432 | 0.35 | 1.42 | 1.41 |