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Table 5 Error test at 100 MHz clock frequency and 633.3 GB of data transferred

From: An inter-FPGA communication bus with error detection and dynamic clock phase adjustment

Error insertion

Amount of

Amount of

Retransmission

rate (error/ms)

inserted errors

retransmitted data (Mb)

time (ms)

1/4

849,871

25.93

∼144