Table 4 Results at 150 MHz
From: An inter-FPGA communication bus with error detection and dynamic clock phase adjustment
Package | Transfer rate | Data amount | Transmission |
|---|---|---|---|
size | (Gbps) | (Gb) | time (s) |
8 | 1.98 | 894.06 | 3600 |
16 | 3.24 | 894.06 | ∼2200 |
32 | 4.76 | 894.06 | ∼1500 |