Table 2 Results at 100 MHz
From: An inter-FPGA communication bus with error detection and dynamic clock phase adjustment
Package | Transfer rate | Data amount | Transmission |
|---|---|---|---|
size | (Gbps) | (Gb) | time (s) |
8 | 1.4 | 633.30 | 3600 |
16 | 2.29 | 633.30 | ∼2200 |
32 | 3.37 | 633.30 | ∼1500 |