Table 1 Results at 50 MHz
From: An inter-FPGA communication bus with error detection and dynamic clock phase adjustment
Package | Transfer rate | Data amount | Transmission |
|---|---|---|---|
size | (Gbps) | (Gb) | time (s) |
8 | 0.7 | 316.65 | 3600 |
16 | 1.14 | 316.65 | ∼2200 |
32 | 1.68 | 316.65 | ∼1500 |